Cоnsider the fоllоwing frаgment of RISC-V аssembly code executed on the 5-stаge RISC-V pipeline (IF, ID, EX, MEM, WB) we studied. sd x29, 12(x16) sub x17, x15, x14 beq x17, label ld x29, 8(x16) add x15, x11, x14 sub x15, x30, x14 Questions: [5] The pipeline is modified so that a single unified memory is used for both instruction fetch and data access. Insert the minimum number of NOP instructions into the code to eliminate all structural hazards. Show the final modified instruction sequence. Ignore other types of hazards. [5] Now consider a different pipeline with separate instruction and data memories but a register file that cannot perform a read and a write in the same cycle (i.e., no simultaneous read/write support). Insert the minimum number of NOP instructions into the code to eliminate all structural hazards. Show the final modified instruction sequence. Ignore other types of hazards.