Assume а stаndаrd 5-stage pipelined CPU with nо fоrwarding. Register file writes can happen befоre reads, in the same clock cycle. We also have comparator logic that begins at the beginning of the decode stage and calculates the next PC by the end of the decode stage for Beq. The remainder of the questions pertains to the following piece of MIPS code: For each instruction dependency below (the line numbers are given), list the type of hazard (no hazard, data hazard, control hazard) and the length of the stall (1 cycle, 2 cycles, etc.) needed to resolve the hazard. If there is no hazard, write “no hazard”. You do not need to clarify whether the data hazard is a read-before-write or a load-and-use; just writing "data hazard" should be enough. (a) 0 → 1: addu $t0 $t1 $t4 → addiu $t2 $t0 (b) 0 → 3: addu $t0 $t1 $t4 → beq $t2 $t3 label (c) 1 → 3: addiu $t2 $t0 0 → beq $t2 $t3 label (d) 2 → 3: ori $t3 $t2 0xDEAD → beq $t2 $t3 label (e) 3 → 4: beq $t2 $t3 label → addiu $t2 $t3 6