Cоnsider the gаte level circuit belоw, with (unit cаpаcitance оf minimum-sized inverter). Answer the questions below. a) Assuming all gates are minimum sized, what is the propagation delay from a to x (tp,ax)? (5 pt) b) Assuming all gates are minimum sized, what is the propagation delay from a to z (tp,az)? (5 pt) c) What is the critical path of the circuit? (5 pt) d) Size the gates on the critical path from part c to minimize the delay. Leave the first stage gate to be minimum-sized. There is no need to further compute the transistor sizes. Assume that branch effort b (or path effort h) is converged after first iteration (no need check, no need to continue the iterations). (15 pt) e) After the resized gates from part d, what is the new propagation delay from a to x (tp,ax,new)? (5 pt) f) After the resized gates from part d, what is the new propagation delay from a to z (tp,az,new)? (5 pt) Make sure to show your work and answers on work paper, including the answer with units, and put a box around the final answers. Only your work paper will be graded.
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