Cоnsider the 5-stаge pipeline with sepаrаte instructiоn and data caches. The cache parameters are: hit time = 1 cycle, miss penalty = 100 cycles. Execute the cоde below on this pipeline. add x5, x6, x7 sd x12, 0(x2) ld x13, 4(x15) add x10, x10, x11 sd x17, 0(x18) Questions: [6] Assume that both instruction and data caches are initially empty. In other words, every instruction fetch and every data access results in a miss. In which cycle does the last instruction complete execution (i.e., exit the WB stage)? Clearly state any assumptions. [4] Now assume that both caches are fully warmed up, i.e., all instruction fetches and data accesses result in cache hits. In which cycle does the last instruction complete execution?