Implement the fоllоwing FSMD (using whаtever mоdel you wаnt). Feel free to reuse the existing vаriables, but declare any new ones that you might need. Register the done output. Only reset done and no other registers. // The following counts the number of cycles that elapse until an// input event x is asserted n times.// inputs: go, n, x// outputs: out, donedone = 0; // Only reset the done signalwhile(1) { while (go == 0); // Initialize state done = 0; count_r = 0; cycles_r = 0; // Store n in register (x is not registered) n_r = n; while(count_r != n_r) { if (n_r == x) count_r ++; cycles_r ++ } // assign output and assert done out = cycles_r; done = 1;} Here is the skeleton code to get you started: module fsmd #(parameter int N_WIDTH = 16, parameter int OUT_WIDTH = 64) ( input logic clk, rst, go, x, input logic [N_WIDTH-1:0] n, output logic [OUT_WIDTH-1:0] out, output done ); logic [N_WIDTH-1:0] count_r, next_count, n_r; logic [OUT_WIDTH-1:0] cycles_r, next_cycles; logic done_r; // BEGIN REGION 1 // END REGION 1 always_ff @(posedge clk or posedge rst) begin // BEGIN REGION 2 // END REGION 2 end always_comb begin // BEGIN REGION 3 // END REGION 3 end endmodule
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